As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems generally include a chipset architecture. The chipset architecture is designed to allow one or more chips, typically a group of integrated circuits, to perform related functions. In one chipset architecture, two chips referred to as a Northbridge chipset and a Southbridge chipset are used to perform these functions.
In a typically Northbridge/Southbridge chipset arrangement, the Northbridge chipset is used to connect a processor to computer memory via the front side bus wherein graphic, peripheral component interconnections (PCI) and level 2 cache functions are performed. The Southbridge chipset controls the input/output (I/O) functions for the system including universal serial bus, system's basic I/O systems (BIOS), interrupt controller and an industry standard architecture (ISA) bus. Because the Southbridge chipset controls the I/O functions, the Southbridge chipset may include an I/O controller hub.
I/O controller hubs receive and direct information between I/O devices via a bus. In order to direct the information to the device, the information including an I/O address or I/O access stored in an I/O range that is must be decoded at the chipset to determine where to send the information. Generally, the I/O range is decoded either positively or subtractively.
Using positive decoding, a distinct I/O range is programmed in the chipset to route all information to a particular device via a particular bus based on the distinct I/O range. However, many chipsets can only program or store a limited number of distinct I/O ranges. Thus, under subtractive decoding, any I/O ranges that are not programmed in the chipset will be automatically forwarded to the bus in a broadcast fashion.
In some instances, a chipset only permits the programming of two distinct I/O decode ranges and only uses positive decoding such that the chipset requires a distinct I/O decode range for each device. However, some devices that reside on the bus typically require a distinct range for full functionality such as Super I/O controller, baseboard management controller (BMC), complex programmable logic device (CPLD), and SmartVu cards. Therefore, all four devices are requiring a distinct I/O range but only two are available.